Polymer coatings are used widely in many markets to provide work functions varying from substrate protection, adhesion onto a range of materials, patterning, and electrical isolation. In demanding applications, polymers are subjected to harsh conditions and are required to meet specific engineering properties.
An area of significant growth in back-end semiconductor processes involving chip connectivity and which require significant amounts of polymer is in the deposition of dielectric coatings. During the manufacture of electronic devices, the metallic routing is well defined and must perform at high conductivity with a low risk of electrical leakage or shorting. These metallic lines and junctions are bordered by insulators of a polymeric variety. These polymers must be deposited with a high degree of uniformity and in some cases, must be thick, typically greater than 5 μm (micron). Further, these dielectric coatings are commonly subject to high temperatures and a wide range of environmental conditions. It is desired to coat substrates with polymer films, which meet these requirements of smoothness, thickness, thermal resistance, and environmental protection.
Typical organic-based dielectrics are chosen from engineering polymers, as these materials comprise high molecular weight substances, offer insulative properties, and resist temperatures and other damaging effects to the microelectronic circuit. Examples of these chemistries include polyimide (PI) and poly-(p-phenylene-2,6-benzobisoxazole) (PBO) as manufactured by Hitachi-DuPont Microsystems (www.hdmicrosystems.com). Another popular organic insulator for electronic applications is bisbenzocyclobutene (BCB), manufactured by the Dow Chemical Company (www.dow.com/cyclotene). Another product that is of a different chemistry, yet is structurally rigid and exhibits resistance character that is common to these families is a photoimageable epoxy, using InterVia™, manufactured by Rohm and Haas (www.rohmhaas.com).
These polymers are applied to the substrate in a similar fashion as a photoresist, using conventional spin and spray coating methods, or they may be slit-coated as is common practice in manufacturing flat panel displays (FPDs). By far, the most common coating method is spin coating. For this reason, the organic-based dielectrics described here may often be referred to as spin-on dielectrics.
In microelectronic manufacturing, spin coating is the method of choice used to apply a thin polymer coating to a substrate. Material is dispensed in the form of a liquid at the center of a substrate and then the coating equipment applies a high rate of circular motion. Liquid delivery may be done by a static method, whereby the fluid will “puddle” onto the surface. A dynamic method may also be used where the material is dispensed when the substrate is already in motion. The substrate spins at a known rotation per minute (rpm), which spreads the polymer fluid over the substrate. As the polymer fluid spreads over the surface, it undergoes dynamic changes in rheology due to solvent evaporation, leading to viscosity increase, and fixing of the polymer onto the surface as a thin coating. The polymer fluid is driven from the center to the edge of the substrate by centrifugal force from the applied motion.
Surface tension describes the nature of substrate wetting, a major contributor to good film formation. A liquid is said to wet a substrate when the substrate has equal or higher surface tension than the liquid itself. Surface tension is the force that holds a liquid together and causes it to occupy the smallest possible volume. This is why atomized liquids, or any which are suspended, will form a bead.
In terms of fluid dynamics, spin coating can be described as the interaction of two bodies, a solid body that is rotating underneath a liquid body. The friction of the rotating body causes dramatic movement outward from the center to the edge by centrifugal force. The liquid continues movement outward until the viscous adhesion of the fluid equals the frictional force of the moving substrate. Viscous adhesion will increase as the resin fluid undergoes evaporation and viscosity increases. With viscosity increase, frictional forces increase with the underlying moving substrate, and the film begins to fix onto the surface. At this point, the frictional forces in the fluid dominate which leads to limited mobility and further condensation. Continued rotational motion leads to further evaporation and densification, the dominant fluid dynamic of the last stage of coating.
As the polymer coats the surface and is driven to the edge, it will eventually be “spun-off” of the substrate and much of the material will collect in the “spin bowl” of the equipment, where it then drains to a waste receptacle. Film thickness, micro- and macro-uniformity, and adhesion will depend on the nature of the resin and the resin mixture (percent solids, viscosity, solvent vapor pressure, etc.) and the parameters chosen for the coating process. A common practice to achieve thick coatings is to increase the percent resin in a coating composition, which invariably increases the viscosity of the coating composition. However, such viscosity increase may result in poor coating performance. In total, the coating process may be viewed as governed by physical-chemical dynamics of wetting, mobility, viscosity, and evaporation.
The manipulation of spin-speed is a common focus of many apparatus used in the microelectronics industry. Substrate rotation will have a direct affect on these properties and produce different coating results. At low spin-speeds, fluid mobility will be low with minor material loss and consequently, coating, fixing, and densification is accelerated, resulting in thicker films, typically measured in microns (1 um=1×10−6 m). However, high spin-speeds will result in high fluid mobility, high material loss, and low fixing and evaporation. High spin-speeds result in thin films, typically measured in angstroms (1 Å=1×10−10 m).
Once the dielectric is applied, it may undergo a patterning process. Patterning may include in-situ exposure of the dielectric due to the presence of photosensitive components, or a secondary coating, which typically comprises a photosensitive material such as photoresist. Once the initial coating is complete and where necessary, patterned, it must be cured to a final-stage, which permanently fixes the material in place to reach the desired chemical and physical properties for performance of the electric circuit. For purposes of this discussion, reference to the organic-based dielectrics includes PI, PBO, BCB, and epoxy. Final curing of these materials typically includes an exposure to high temperature for periods of time. This curing allows for a chemical condensation reaction to occur where high density polymeric cross-linking takes place. In the case of PI, an imidization process produces the high molecular weight of the final species. Process temperature exposures are common at 200° C., and many times, will require up to 300° C., depending upon the holding time. Interdependence exists between temperature and time, whereby it is common to have lower temperature exposures at 200° C. but require an excess of 3 hrs baking time.
The number of metals and substrates used in microelectronics vary, and for this reason, additional handling practices must be instituted to minimize cracking, loss in adhesion, or other failures. These added practices include reducing temperature shock by extending the process time for heating and cooling, allowing for differences in material coefficients of thermal expansion. The high temperature bake at an extended time represents a process challenge in microelectronic manufacturing.
Once a dielectric coating that comprises PI, PBO, BCB, or epoxy is fully cured, it is considered to be permanent, whereby, the need for rework would either require the use of aggressive materials such as strong acids or bases, or mechanical removal. Such aggressive methods would likely attack and/or destroy the substrate or adjacent metals. More practically, once these systems are final cured, a rework condition would be considered as not commercially available.
It is therefore desirable to have a polymer coating, which exhibits fundamental thermal resistance as its property and is able to support the application of smooth and thick coatings that are cured at lower temperatures following a rapid process; once cured, the coating is preferred to support simple rework practices.
Another area in microelectronic manufacturing where thick polymer films, which exhibit thermal resistance are needed, is the practice of wafer thinning. Substrate thinning is a standard practice in the fabrication of microelectronic devices. A thinned substrate is used to enhance cooling of the device during its operation as a chip in a computer, cell phone, or other end use electronic component such as an appliance. Another purpose of thinning is to enable thin substrate stacking, for example, as in three dimensional (3-D) packaging (i.e. chip stacking), and to reduce the mass of the final product. The requirement of thermal resistance is needed to support backside processing of the thinned substrate. The backside processing practices of thermal resistance include the etching of through silicon vias (TSV) or deposition of silicon oxide, whereby temperatures during chemically assisted plasma or evaporative deposit processing may exceed 300° C. TSV and related backside steps allow connectivity between stacked chips.
In IC manufacturing, there is a continued demand to miniaturize devices while a growing desire also exists to stack chips (i.e. 3-D packaging). Achieving these objectives is limited by the ability to reduce the substrate to ultra-thin dimensions. To fully appreciate this need, it is necessary to consider the common and generally accepted phenomena that most, if not all ICs, generate heat as a byproduct of their function and will perform less than ideally with such heat exposure. In a conventional IC, only a minor proportion of the substrate is used for its performance. Since semiconductors are poor thermal conductors, they will store the generated heat in their mass. As more heat is produced, more is stored, until a physical limit is reached in the electrical circuit at which efficiencies drop and errors occur. To maintain proper IC function, heat must be continually removed as it is generated.
The common method for IC cooling (i.e. heat removal) is to install blowers, which dissipate heat from the printed wire board (PWB). For miniaturized ICs, this means of removing heat is impractical. Hand-held devices such as calculators, cell phones, pagers, and others must depend upon dissipation of heat through conduction. For best results, the IC substrate is thinned and brought into direct contact with a heat conducting medium, e.g. heat sink. As the IC's heat is generated, it is conducted away (dissipated) by intimate contact with a comparatively large heat sink.
Not only does wafer thinning help to dissipate heat, but it also aids in the electrical operation of the IC. Substrate thickness affects impedance and capacitance performance of certain connecting leads, e.g. transmission lines, of given thickness from the top of the IC to the bottom where contact is made to the PWB. Thick substrates cause an increase in capacitance, requiring thicker transmission lines, and in turn, a larger IC footprint. Substrate thinning increases impedance while capacitance decreases, causing a reduction in transmission line thickness, and in turn, a reduction in IC size. In other words, substrate thinning facilitates IC performance and miniaturization.
An additional incentive in support of substrate thinning involves geometric reasons. Via-holes are etched into the backside of an IC device wafer to facilitate front side contacts. In order to construct a via-hole (hereafter sometimes referred to as a “via” or “vias”) using common dry-etch techniques, minimum geometrical design standards apply. Namely, for IC substrates of the gallium arsenide (GaAs) type with thicknesses of <100 μm, a 30-70 μm diameter via may be constructed using dry-etch methods that produce minimal post-etch residue within an acceptable time. In silicon substrates of thicknesses of <25 μm, vias of much smaller diameter of <10 μm, sometimes referred to as through silicon vias (TSVs), are used for communication between stacked chips in 3-D packaging. Due to the complexity of silicon ICs, many TSVs are required for connectivity. As substrates are thinned further to smaller dimensions, smaller diameter vias may be used, requiring shorter etch times, producing smaller amounts of post-etch residue, and promoting greater throughput. Smaller vias require less metallization and in turn, lower cost. Therefore, from the standpoint of backside processing, thin substrates are processed quicker and at lower cost.
A final consideration in support of thin substrates is that they are more easily cut and scribed into devices. Thinner substrates have a smaller amount of material to penetrate and cut, and therefore require less effort. Whether the method used is sawing, scribe and break, or laser ablation, microelectronic devices are easier to cut from thinner substrates.
Examples of final products in microelectronics where there exists a desire to thin substrates includes integrated circuits (IC), microelectromechanical systems (MEMS), and large irregular panel dimensions as in flat panel displays (FPD) and solar substrates. Manufacturing ICs and MEMS are typically conducted upon wafers of standard diameters that are composed of silicon or a compound semiconductor species and are taken to ultra-thin values (i.e. <20 μm) and subsequently stacked to achieve designs in 3-D packaging. Where FPDs and solar panels are concerned, thinned substrates of various shapes are required to reduce weight to meet ergonomic objectives of the final customer package. Conventional technologies for achieving thin device substrates include mechanical grinding and chemical etching, and where ultra-thin dimensions are in demand, various protecting and handling materials are used, including tapes, coatings, and externally mounted rigid supports (i.e. carriers).
Wafer thinning to dimensions of <50 μm substrate thickness, although being a common practice in the manufacture of high power chips of the variety of compound semiconductor designed for radio-frequency emittance (e.g. cell phones, radar, etc.), has not been in high volume production, rather, it is done in limited numbers for special applications. With the need for thin silicon emerging, high volume wafer thinning down to ultra-thin levels is now a commercial target. Wafer thinning requires complete planarization of the wafer topography, with device geometries exceeding 10 μm (microns). It is desired to have a method of coating thick polymers onto this surface, which leads to planarization and wafer thinning support.
As with any new technology, there is always a question of scaling. Within the practice of wafer thinning, discussion surrounds the need to reduce the thickness of the chip to a level that approaches the operating topography of the device. Customary wafer thicknesses during front-end device manufacture begin in the range of 600-700 μm. In many cases, thinning objects must take this dimension to below 20 μm (microns). When this occurs, preparation for handing thin substrates must be included.
In the case where a microelectronic device is manufactured on a wafer, the substrates are thinned after wafer front side operations are complete. In this case, the devices are fabricated onto wafers that exist at their normal full-size thickness, e.g. 600-700 μm (0.024-0.028″). Once completed, they are thinned to 100-150 μm (0.004-0.006″). In some cases, as in hybrid substrates used for high power devices, e.g. Gallium Arsenide (GaAs), thickness may be taken down to <20 μm (<0.001″).
Substrate thinning may be performed by mechanical or chemical means. In a mechanical thinning process, the substrate surface to be thinned is brought into contact with a hard and flat rotating horizontal platter, which may or may not contain liquid slurry. The equipment may be referred to as a “grinder” or a “coarse polisher”. When slurry is used, it may contain abrasive media with chemical etchants such as ammonia, fluoride, or the combinations thereof. The abrasive operates as a “coarse” substrate removal practice, to thin the substrate, while the etchant chemistry facilitates “polishing” at the submicron level.
Thinning may also be performed by chemical etching. Unlike mechanical processing, substrates enter a tank containing a chemical etchant. Substrates are thinned by the action of a vigorous chemical reaction with the substrate composition. For example, silicon may be etched at rapid rates using a mixture of nitric acid with levels of fluoride present, or by the use of a strong alkali such as potassium hydroxide. Chemical etch rates are typically more difficult to control due to their high rates of removal, which may approach 100 μm per minute. Where bath control is needed to achieve greater uniformity, a diluted chemistry with temperature controls is common practice.
In either cases of mechanical and chemical thinning, the substrate is maintained in contact with the media until an amount of material has been removed to achieve a targeted thickness. For a final thickness of 100 μm or greater, the substrate is held directly with tooling that utilizes a vacuum chuck or some means of mechanical attachment. While it is of interest to achieve substrate thinning, it is simultaneously an objective to protect the device areas during such processing. Protection of the device area may occur by a sealed vacuum chuck, an adhesive film (i.e. tape), or a polymer coating. Once the process is completed, the film or coating must be removed.
Conventional methods to achieve thinning are limited by the ability to handle fragile substrates, and when pursuing the very thin, there is a requirement to use external support structures. Where economic limitations exist, external supports are not used, whereby the choice in final thickness is then dependent upon the ability to handle thin substrates in a tool. However, for achieving thin substrates (i.e. <100 μm), it becomes difficult or impossible to maintain control, e.g. attachment and handling, by making such contact directly to the substrate. In some cases, mechanical devices may be made to attach and hold onto thinned device substrates, however, they are subject to many problems, especially when processes vary. For these reasons, the substrates may be temporarily mounted onto separate rigid supports (carriers). The external temporary support (i.e. carrier) is mounted to the wafer to allow ease of handling during thinning and backside processing. These temporary mounted carriers become the holding platform to allow a tool to grab and secure the device substrate to support thinning, resist pattering, plasma etching, post-etch residue cleans, and metallization.
Temporary mounted carriers may include sapphire, quartz, certain glasses, and silicon. They usually exhibit a thickness of 1000 μm (1 mm or 0.040″). Substrate choice will depend on how closely matched the coefficient of thermal expansion (CLTE) is between each material. Although it is common to use transparent carriers such as sapphire, quartz, and glass, some cost sensitive processes may use silicon with an alternative practice to the use of visible light microscopy for locating alignment markers or conducting inspection. Where necessary, carrier substrates may be produced with holes, channels (e.g. grooves), or other similar designs. These specially designed carriers offer an enhanced transport of chemical fluids to the surface of the substrate in order to accelerate demount.
All external carriers require the use of an adhesive for mounting onto the device substrate. The adhesive becomes incorporated into the substrate-carrier package, whereby its properties must exhibit thermal resistance to be accepted into the steps of thinning and backside processing.
Mounting of the external carrier to the semiconductor wafer can be a lengthy and a delicate process. During mounting, the device substrate and potentially the external carrier is coated with the adhesive, brought into direct contact with each other, and cured to a level sufficient to secure both surfaces. Attention must be given to the adhesive's ability to planarize the device surface such that the topography is fully encapsulated and protected within the wafer-carrier package. During mounting, excessive pressures may be applied. A special tool may be used, commercial devices are classed as bonding equipment (e.g. bonders). Depending upon the adhesive, the mounting process may utilize heat, light exposure, pressure, or any variety of these together, to achieve cure and facilitate a securely mounted substrate and carrier. The adhesive must maintain a rigid network such that no mechanical compromise occurs (e.g. movement) and any reference points required during mounting are identified and preserved. The maximum temperature exposed to the substrate-carrier package occurs in wafer backside processing during resist baking, via etching, and the deposition of certain metals or oxides.
Demount (i.e. debonding) is the reverse process, involving the separation of the external carrier from the device substrate by a means of chemical, mechanical, or processes that involve the combination thereof. Chemical demounting requires the use of perforated support substrates, specially fabricated to increase the rate of chemical penetration leading to dissolution and removal of the mounting adhesive. In this process, the chemistry of choice is an organic solvent that is heated and allowed to diffuse into the holes (perforations) or channels (grooves), as well as the bond line between the external carrier and device substrate. The organic solvent will swell and dissolve the temporary adhesive to such a level which effects demounting of the external carrier, as well as the removal of residual adhesive on the device substrate surface. These chemicals are needed in quantities necessary to support a cleaning process, whereby the substrates travel from one heated bath to another in an effort to demount the external carrier and remove the adhesive to deminimus levels on the device substrate and result in a clean surface. The entire demount may be measured in terms of 30 minutes to several hours, depending upon the use of heat and agitation.
Alternatively, thermo mechanical demounting may be achieved with thermoplastic adhesives. As taught in U.S. Pat. No. 6,792,991 B2, Thallner, and U.S. Patent Application No. 2007/0155129 (2007), Thallner, separation may be achieved by heating the wafer-carrier package to a temperature above the melting point of the adhesive while simultaneously applying a shear force in a manner designed to separate the mounted surfaces. In other words, the device substrate is removed from the external support carrier by heat and a mechanical force of a predetermined amount and in an orientation sufficient to slide the two surfaces in a shear direction. Cleaning with a selected organic solvent typically follows to ensure residual adhesive is cleaned from the substrate.
Mechanical separation is observed to be faster than a chemical demount process. However, specially designed tools must be used to mechanically remove a thinned device substrate from the external carrier without damage to the topography. Although mechanical removal may proceed faster than chemical, a true comparison should consider total throughput. For example, a chemical demount process is typically done by a batch process where two or more cassettes of twenty-five (25) wafers each are accommodated in a bath. A mechanical tool designed for shear separation (i.e. slide function) typically operates as a single wafer operation. Process time of a batch chemical diffusion driven demount which use perforated carriers could take up to 3 hrs, however, there may be 50 wafers at a time in the bath. Therefore, for a process time of anywhere between 2-4 min for a single wafer process, the overall throughput is comparable to a batch driven process that takes 3 hrs. Further, there is an increased risk in substrate damage when using a mechanical device that moves or pulls the microelectronic substrate against the surface of the external support carrier. Where there may be an interest to consider mechanical equipment, the adoption must meet the requirements and cost constraints of the process.
Another desire of the adhesive is to exhibit good chemical resistance to diluted aqueous chemistries of various characteristics. This must be established for a range of chemistries from strong etchants used in post-thinning stress relief such as sulfuric, ammonia, and/or peroxide, as well as organic solvents used in the lithography and clean steps during via-hole processing. Ideally, the adhesive must be resistant to these process chemistries, yet be selectively dissolved and removed at the end of the manufacturing process line. At times, certain aggressive chemistries may be chosen which have detrimental effects on the adhesive. As such, some temporary manufacturing measures may be taken to include protective tape or other coverings.
A review of the adhesive properties used to support device substrate thinning and backside engineering processes in microelectronic manufacturing presents serious and compelling challenges. In U.S. Pat. No. 7,098,152 (2006), Moore, teaches a process of using an external temporary carrier with an adhesive coating which is based upon mixtures of rosins and urethanes. Further description of this rosin-urethane chemistry and its application to wafer thinning are disclosed in U.S. Pat. No. 6,869,894 (2005), Moore, and in Mould, D., and Moore, J., A New Alternative for Temporary Wafer Mounting, GaAs ManTech Conf. and Proc., pp. 109-112, (2002). The compositions and practices identified in these references provide the necessary conditions as an adhesive coating that is thermally resistant up to and including 130 degrees centigrade (130° C.).
Mounting adhesives based upon the use of silicone rubber compounds and used in the manner to apply external temporary carriers to silicon and compound semiconductor wafers are disclosed in U.S. Pat. No. 7,232,770 (2007), Moore et al., and the publication by Moore, J., Smith, A., and Kulkami, S., High Temperature Resistant Adhesive for Wafer Thinning and Backside Processing, GaAs ManTech Conf. and Proc., pp. 175-182, (2004). These documents describe the use of a high temperature resistant adhesive based upon silicone compounds, which may be processed at temperatures exceeding 200 degrees centigrade (200° C.).
Another adhesive composition disclosed in U.S. Patent Application No. 2007/0185310 A1 (2007), Moore et al., where thermal and chemical resistant coatings are taught based upon the use of ethylene propylene diene monomer (EPDM) and related hydrocarbon rubber compounds. These documents describe a process for adhering external temporary carriers to semiconductor wafers, and once cured, are observed to withstand processing temperatures that exceed 200 degrees centigrade (200° C.) and are resistant to polar solvents commonly used in semiconductor fabrication areas, such as n-methyl pyrollidone (NMP).
Another adhesive system for substrate thinning which uses external carrier supports, is described in the U.S. Patent Applications 2009/0017248 A1 (2009), Larson et al., 2009/0017323 A1 (2009), Webb et al., and in the International Application WO 2008/008931 A1 (2008), Webb et al. These documents describe the use of a layered body that is formed which comprises the substrate being attached to an external carrier support. The adhesive described is a bilayer system composed of a photothermal conversion layer and a curable acrylate. Typical acrylic chemistries are not categorically considered to be engineering polymers, and therefore, do not exhibit the quality of thermal resistance. In review of the U.S. Patent applications 2009/0017248 A1 (2009), 2009/0017323 A1 (2009), and in the International Application WO 2008/008931 A1 (2008), the value of thermal resistance for the layered body is not mentioned. Nevertheless, those who are skilled in the art would generally accept a maximum thermal resistance range for unfilled acrylic polymers to be <200° C. for process durations sufficient to support wafer thinning applications. We emphasize “unfilled”, as it is not mentioned in the U.S. Patent applications 2009/0017248 A1 (2009), 2009/0017323 A1 (2009), and in the International Application WO 2008/008931 A1 (2008), that the acrylic systems in practice use engineering fillers.
The aforementioned polymer compositions as described here in U.S. Pat. No. 6,869,894 (2005), Moore, U.S. Pat. No. 7,232,770 (2007), Moore et al., U.S. Patent Application No. 2007/0185310 A1 (2007), Moore et al., and the combined descriptions of U.S. Patent Applications 2009/0017248 A1 (2009), Larson et al., 2009/0017323 A1 (2009), Webb et al., and in the International Application WO 2008/008931 A1 (2008), Webb et al., all describe traditional methods of attaching an external carrier support made of glass, sapphire, or silicon to a wafer using adhesive chemistries: a thermoplastic rosin-urethane, a thermoset silicone, a thermoplastic rubber, and a thermoset acrylic, respectively. The thermal resistance as reported in these documents or otherwise investigated does not significantly exist above the value of 200° C.
It is therefore desirable to have a polymer coating, which exhibits the fundamental property of thermal resistance that significantly exceeds 200° C., preferable to beyond 300° C., and is able to perform as a temporary adhesive to mount semiconductor wafers to external carrier substrates, support the application of wafer thinning and backside processing, and finally, to demount and clean with simple chemistries at acceptable process conditions.
The engineering polymer, polybenzimidazole (PBI), provides key engineering properties such as a high temperature resistance, indicated by a high glass transition (Tg>435 degrees centigrade), and low coefficient of thermal expansion (CTE<23 ppm). Other noteworthy properties and uses for PBI include protective films as presented in the report, “History and Development of Polybenzimidazoles,” authored by E. J. Powers and G. A. Serad, presented at the Symposium on the History of High Performance Polymers, American Chemical Society, New York, Apr. 15-18, 1986. The use of PBI as a coating has been limited by poor stability as a pure organic solution (i.e. PBI dissolved in organic solvents) and poor adhesion to hard substrates when it is coated and cured. See for example U.S. Pat. No. 5,549,946 (1996), Iura, et al., and U.S. Pat. No. 5,674,614 (1997), Onishi, et al.
While there is a desire to address the need for a high temperature resistant form of PBI which exhibits sufficient stability without the use of metallic stabilizers and will perform as a smooth coating onto microelectronic devices with a rapid cure at moderate temperatures for use as a dielectric, there also, is a challenge to address the need for a thermal resistant adhesive form of PBI to support thinning and backside processing of device substrates of various sizes and shapes. Taking these challenges together, there is a pressing need to provide a consistent and universal product, which uses a composition that comprises PBI and meets the objectives of a thermal resistant coating that is able to coat a range of substrates and thicknesses, and depending upon these application conditions, is sufficient to be classified as a dielectric and/or adhesive for wafer thinning and backside processing.